Applications are invited for the following temporary post to work on the C2S project (Category III) sponsored by MeitY entitled “Instruction-Data level Parallelism based Hardware Accelerator Design in HPC and CPS Applications”.
| Name of the Post | Junior Research Fellow |
| Number of posts | Two |
| Nature of the post | The post is purely temporary and is for the duration of one year. It may be extended for another one/two year(s) or till the completion of the project depending on the requirement and the performance of the candidate. |
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Minimum Qualification and Experience |
B.E/ B.Tech in Electrical/ Electronics Engineering with GATE qualified at any time. AND/ OR M.E/ M.Tech in Microelectronics/ VLSI design with GATE qualified at any time. |
| Desirable Qualification and Experience | Candidate having experience in Digital System Design, RTL design using Verilog/VHDL, IP integration using Xilinx Vivado, Custom IP development using Xilinx Vivado, and Semi Custom ASIC design using EDA tools. |
| Salary | Rs. 37,000 per month (consolidated) |
| Ph.D. Opportunity | JRF candidate selected for this position will have the opportunity to register for regular Ph. D. program in IIITDM Kurnool provided JRF satisfies the eligibility criteria for the same. |
| Mode of Application | The duly filled/signed application along with the copy of the necessary testimonials should be sent by the post to the Principal Investigator of this project. OR The scanned copy of the duly filled/signed application along with the necessary testimonials should be sent by Email to the Chief Investigator (CI) of this project. |
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Correspondence Address of Chief Investigator |
Dr. Mohamed Asan Basiri M, Department of ECE, IIITDM Kurnool, Jagannthagattu, Kurnool, Andhra Pradesh – 518007, Email – [email protected] |
| Important Dates |
The last date of receipt of the completed application form is 11 March 2024. Mode of selection: Written Test/Interview The date of Written Test/Interview will be informed to the shortlisted candidates by email. |
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